A phase locked loop (PLL) is used to synchronize signals. PLLs are used in radio transceivers, telecommunications, clock multipliers, microprocessors and other devices which use synchronized signals. PLLs are used to synchronize the signals of two separate devices. As technology advances, a wider range of frequencies is used to synchronize separate devices. Also, as chip switching speed increases, a faster locking time for synchronizing signals of the two separate devices is desired. However, prior PLL designs exhibit a slow locking time, increased power consumption or increased chip size.
Prior techniques for using a PLL to lock two signals together in synchronization include wide-range digital logic quadricorrelator (WDLQ) based systems. WDLQ based systems have a long processing time, resulting in a slow locking time in comparison with other techniques. A counter based system exhibits a faster locking time than the WDLQ based system, but requires the inclusion of a high frequency clock and a counter which increases power consumption and chip size.